1. Technical Field
The present invention relates to a semiconductor memory apparatus, and more particularly, to a circuit for generating negative voltage and a semiconductor memory apparatus using the same.
2. Related Art
FIG. 1 is a schematic block diagram of a conventional circuit for generating negative voltage. in FIG. 1, a circuit 1 for generating negative voltage includes a detecting unit 10, an oscillator 20, and a pump 30.
The detecting unit 10 enables a detection signal ‘det’ when the level of negative voltage VBB becomes higher than a target level. Conversely, the detecting unit 10 disables the detection signal ‘det’ when the level of the negative voltage VBB becomes lower than the target level.
The oscillator 20 generates an oscillator signal ‘OSC’ in response to the detection signal ‘det’. For example, when the detection signal ‘det’ is enabled, the oscillator 20 generates the oscillator signal ‘OSC’. When the detection signal ‘det’ is disabled, the oscillator 20 fixes the oscillator signal ‘OSC’ to a specific level.
The pump 30 performs pumping operations in response to the oscillator signal ‘OSC’, and generates the negative voltage VBB by pumping operations. Here, the pump 30 is constructed to perform pumping operations synchronous to the time when the oscillator signal ‘OSC’ transitions from high level to low level or from low level to high level.
The generated negative voltage VBB is supplied to a bulk node of an NMOS transistor that generally includes a word line driver or a cell transistor array.
Due to voltages individually supplied to a gate terminal or a drain terminal of the NMOS transistor, a gate-induced drain leakage (GIDL) current may flow from the drain region or the gate terminal to the bulk node. Due to the gate-induced drain leakage current, the level of the negative voltage VBB may increase. More specifically, if the amount of the gate-induced drain leakage current becomes larger than the current supply capability of the pump 30, then the negative voltage VBB increases without maintaining the target level. The gate-induced drain leakage current is a leakage current flowing between a drain region and a bulk node of the NMOS transistor due to hole components of electron-hole pairs (EHPs), which are generated in the drain region when electric fields of a gate terminal and the drain region of an NMOS transistor in a turned-OFF state are strengthened.